Inovasi Spasi Udara IBM Membuka Jalan untuk Chip FinFET 10nm

Ini adalah bagian ketiga dari seri empat bagian tentang makalah canggih IBM yang disajikan di IEDM 2016.

International Electron Devices Meeting widely regarded as world’s premier forum for breakthrough research in semiconductor and electronic device technology, design, manufacturing, physics, and modeling. At this year’s conference in San Francisco, IBM showcased scanning-probe thermometer, air-spacer technique for 10 nm chips, 7 nm device, and even carbon nanotube innovations—all aimed at extending Moore’s Law and exploring new architectures.

Among four highlighted IBM papers, third focuses on “Air Spacer for 10 nm FinFET CMOS and Beyond.” Dr. Kangguo Cheng, senior technical staff member and Master Inventor at IBM Research’s Albany Nanotech Center, led team that demonstrated how a simple air gap can dramatically lower parasitic capacitance in next-generation transistors.

While 14 nm nodes are already manufacturable, transition to 10 nm faces a critical obstacle: parasitic capacitance. As transistors shrink, insulating gaps between contacts become proportionally smaller, allowing unwanted charge to accumulate. When a transistor switches, this stored charge is released, causing slower signal propagation and higher power consumption—ultimately leading to increased heat and reduced reliability.

Dr. Cheng’s approach replaces these conductive gaps with air—an almost perfect insulator. By inserting an air spacer above the fin top, the team reduced transistor-level capacitance by up to 25 % and achieved a 15 % reduction in a ring-oscillator test circuit. The result is a 25 % power savings at the device level and a corresponding 15 % system-wide improvement.

Kiri atas: Gambar TEM transistor FinFET dengan spasi udara (ruang putih) pada dimensi 10 nm. Kanan atas: Kerusakan setelah proses pulldown spasi yang agresif; khususnya, erosi fin dan epitaksi source/drain. Tengah bawah: Skematik struktur spasi udara parsial. Spasi udara hanya terbentuk di atas ujung fin untuk meminimalkan dampak pada gate stack. Liner dielektrik melindungi gate stack selama pembuatan spasi udara.

By mitigating parasitic capacitance, air spacers enable more efficient 10 nm and 7 nm FinFET chips, and they hold promise for power-saving 14 nm devices as well. IBM’s work illustrates how a material as simple as air can play a pivotal role in next-generation semiconductor design.

Baca bagian satu: Mapping hot spots
Baca bagian dua: Chip lain dengan karbon nanotube