Desain Tingkat Gerbang Praktis Verilog: Gerbang AND, OR, NOT & Multiplexer 2x1

Beberapa primitive built-in utama telah dibahas dalam artikel sebelumnya dan akan baik untuk melihat beberapa contoh praktis penggunaan gerbang and, nor dan not sederhana.

Perhatikan bahwa untuk menulis kode Verilog menggunakan gerbang, Anda perlu mengetahui cara menghubungkan elemen-elemen tersebut. Ini sangat berbeda dari deskripsi perilaku di mana pemilihan dan koneksi elemen diserahkan pada alat sintesis.

Contoh #1: Multiplexer 2x1

Output modul harus bertipe wire agar dapat terhubung dengan port output primitive.

module mux_2x1 (
  input a, b, sel,
  output out
);
  wire sel_n;
  wire out_0;
  not (sel_n, sel);
  and (out_0, a, sel);
  and (out_1, b, sel_n);
  or (out, out_0, out_1);
endmodule

module tb;
  reg a, b, sel;
  wire out;
  integer i;
  mux_2x1 u0 (
    .a(a), .b(b), .sel(sel), .out(out)
  );
  initial begin
    {a, b, sel} <= 0;
    $monitor ("T=%0t a=%0b b=%0b sel=%0b out=%0b", $time, a, b, sel, out);
    for (int i = 0; i < 10; i = i+1) begin
      #1 a <= $random; b <= $random; sel <= $random;
    end
  end
endmodule

Log Simulasi

ncsim> run
T=0 a=0 b=0 sel=0 out=0
T=1 a=0 b=1 sel=1 out=0
T=2 a=1 b=1 sel=1 out=1
T=3 a=1 b=0 sel=1 out=1
T=6 a=0 b=1 sel=0 out=1
T=7 a=1 b=1 sel=0 out=1
T=8 a=1 b=0 sel=0 out=0
T=9 a=0 b=1 sel=0 out=1
T=10 a=1 b=1 sel=1 out=1
ncsim: *W,RNQUIE: Simulation is complete.

Penambal Lengkap

module fa (
  input a, b, cin,
  output sum, cout
);
  wire s1, net1, net2;
  xor (s1, a, b);
  and (net1, a, b);
  xor (sum, s1, cin);
  and (net2, s1, cin);
  xor (cout, net1, net2);
endmodule

module tb;
  reg a, b, cin;
  wire sum, cout;
  integer i;
  fa u0 (
    .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout)
  );
  initial begin
    {a, b, cin} <= 0;
    $monitor ("T=%0t a=%0b b=%0b cin=%0b cout=%0b sum=%0b", $time, a, b, cin, cout, sum);
    for (i = 0; i < 10; i = i+1) begin
      #1 a <= $random; b <= $random; cin <= $random;
    end
  end
endmodule

Log Simulasi

ncsim> run
T=0 a=0 b=0 cin=0 cout=0 sum=0
T=1 a=0 b=1 cin=1 cout=1 sum=0
T=2 a=1 b=1 cin=1 cout=1 sum=1
T=3 a=1 b=0 cin=1 cout=1 sum=0
T=6 a=0 b=1 cin=0 cout=0 sum=1
T=7 a=1 b=1 cin=0 cout=1 sum=0
T=8 a=1 b=0 cin=0 cout=0 sum=1
T=9 a=0 b=1 cin=0 cout=0 sum=1
T=10 a=1 b=1 cin=1 cout=1 sum=1
ncsim: *W,RNQUIE: Simulation is complete.

Dekoder 2x4

module tb;
  reg x, y, en;
  wire a, b, c, d;
  integer i;
  dec_2x4 u0 (
    .x(x), .y(y), .en(en), .a(a), .b(b), .c(c), .d(d)
  );
  initial begin
    {x, y, en} <= 0;
    $monitor ("T=%0t x=%0b y=%0b en=%0b a=%0b b=%0b c=%0b d=%0b", $time, x, y, en, a, b, c, d);
    en <= 1;
    for (i = 0; i < 10; i = i+1) begin
      #1 x <= $random; y <= $random;
    end
  end
endmodule

Log Simulasi

ncsim> run
T=0 x=0 y=0 en=1 a=0 b=0 c=0 d=1
T=1 x=0 y=1 en=1 a=0 b=0 c=1 d=0
T=2 x=1 y=1 en=1 a=1 b=0 c=0 d=0
T=4 x=1 y=0 en=1 a=0 b=1 c=0 d=0
T=5 x=1 y=1 en=1 a=1 b=0 c=0 d=0
T=6 x=0 y=1 en=1 a=0 b=0 c=1 d=0
T=7 x=1 y=0 en=1 a=0 b=1 c=0 d=0
T=10 x=1 y=1 en=1 a=1 b=0 c=0 d=0
ncsim: *W,RNQUIE: Simulation is complete.

Encoder 4x2

module enc_4x2 (
  input a, b, c, d,
  output x, y
);
  or (x, b, d);
  or (y, c, d);
endmodule

module tb;
  reg a, b, c, d;
  wire x, y;
  integer i;
  enc_4x2 u0 (
    .a(a), .b(b), .c(c), .d(d), .x(x), .y(y)
  );
  initial begin
    {a, b, c, d} <= 0;
    $monitor("T=%0t a=%0b b=%0b c=%0b d=%0b x=%0b y=%0b", $time, a, b, c, d, x, y);
    for (i = 0; i <= 16; i = i+1) begin
      #1 {a, b, c, d} <= i;
    end
  end
endmodule

Log Simulasi

ncsim> run
T=0 a=0 b=0 c=0 d=0 x=0 y=0
T=2 a=0 b=0 c=0 d=1 x=1 y=1
T=3 a=0 b=0 c=1 d=0 x=0 y=1
T=4 a=0 b=0 c=1 d=1 x=1 y=1
T=5 a=0 b=1 c=0 d=0 x=1 y=0
T=6 a=0 b=1 c=0 d=1 x=1 y=1
T=7 a=0 b=1 c=1 d=0 x=1 y=1
T=8 a=0 b=1 c=1 d=1 x=1 y=1
T=9 a=1 b=0 c=0 d=0 x=0 y=0
T=10 a=1 b=0 c=0 d=1 x=1 y=1
T=11 a=1 b=0 c=1 d=0 x=0 y=1
T=12 a=1 b=0 c=1 d=1 x=1 y=1
T=13 a=1 b=1 c=0 d=0 x=1 y=0
T=14 a=1 b=1 c=0 d=1 x=1 y=1
T=15 a=1 b=1 c=1 d=0 x=1 y=1
T=16 a=1 b=1 c=1 d=1 x=1 y=1
T=17 a=0 b=0 c=0 d=0 x=0 y=0
ncsim: *W,RNQUIE: Simulation is complete.